You are here

CEA

CEA

TREFL test bed project
 

Objective

The objective of this project was to develop the software for managing the TREFL test bed for ASIC components (memory chips, sequencers, hyperfrequency components, etc.).

Features

A component test involves sending a configuration bitstream and, during the actual test, setting the inputs in a pre-defined sequence and recording timestamped state changes of the outputs. These state changes are then compared to a chart in order to analyze the test results.

Input signals must be applied with very accurate timing—down to a few nanoseconds—and timestamps on the output state changes must be accurate to 200 ns. Therefore the solution includes an intermediate time-based FPGA board (Altera from the Flex10K product line).
Output state changes are stored on a FIFO basis and provided to the test bed PC at the end of the test. Each test averages one minute.